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1、1,中科院研究生院課程：VLSI測試與可測試性設(shè)計,第5講 測試生成(1) 李曉維 中科院計算技術(shù)研究所 Email: ,2,Chapter 4,Test Generation,3,What is this chapter about?,Introduce the basic concepts of ATPG Focus on a number of combinational and sequential ATPG techniques Deterministic ATPG and simulation-based ATPG Fast untestable fault identificat
2、ion ATPG for various fault models,4,Test Generation,Introduction Random Test Generation Theoretical Foundations Deterministic Combinational ATPG Deterministic Sequential ATPG Untestable Fault Identification Simulation-based ATPG ATPG for Delay and Bridge Faults Other Topics in Test Generation Conclu
3、ding Remarks,5,Introduction,Test generation is the bread-and-butter in VLSI Testing Efficient and powerful ATPG can alleviate high costs of DFT Goal: generation of a small set of effective vectors at a low computational cost ATPG is a very challenging task Exponential complexity Circuit sizes contin
4、ue to increase (Moores Law) Aggravate the complexity problem further Higher clock frequencies Need to test for both structural and delay defects,6,Conceptual View of ATPG,Generate an input vector that can distinguish the defect-free circuit from the hypothetically defective one,7,Fault Models,Instea
5、d of targeting specific defects, fault models are used to capture the logical effect of the underlying defect Fault models considered in this chapter: Stuck-at fault Bridging fault Transition fault Path-delay fault,8,Simple illustration of ATPG,Consider the fault d/1 in the defective circuit Need to
6、 distinguish the output of the defective circuit from the defect-free circuit Need: set d=0 in the defect-free circuit Need: propagate effect of fault to output Vector: abc=001 (output = 0/1),9,Example 1,10,A Typical ATPG System,Given a circuit and a fault model Repeat Generate a test for each undet
7、ected fault Drop all other faults detected by the test using a fault simulator Until all faults have been considered Note 1: a fault may be untestable, in which no test would be generated Note 2: an ATPG may abort on a fault if the resources needed exceed a preset limit,11,Category of ATPG,Simulatio
8、n-based Exhaustive Random-pattern generation Pseudo-random-pattern generation Path sensitization D-algorithm, 9-V algorithm PODEM, FAN TOPS, SOCRATES Boolean satisfiability Select a primitive D-cube of the fault to be the test cube; Put logic outputs with inputs labeled as D (D) onto the D-frontier;
9、 D-drive (); Consistency (); return ();,46,D-frontier,Fault Cone - Set of hardware affected by fault D-frontier Set of gates closest to POs with fault effect(s) at input(s),47,Singular Cover Example,Minimal set of logic signal assignments to show essential prime implicants of Karnaugh map,48,D-Cube
10、Operation of D-Intersection,49,Concluding Remarks,Covered a number of topics Theoretical Foundations Combinational & sequential ATPG Untestable fault identification Simulation-based & hybrid ATPG Delay testing Bridging fault testing Compaction, N-Detect, FSM testing Challenges Ahead Fast untestable fault identification essential to remove large numbers of stuck-at, bridge, delay faults Sequential ATPG remains an open research area,50,中科院研究生院課程：VLSI測試與可測試性設(shè)計,下次課預告 時間：2007年10月29日（周一7:00pm） 地點：S106室 內(nèi)容：測試生成(2) 教材：VLSI TEST PRINCIPLES AND ARCHITECTURES Chapter 4 Test Generation,51,
中科院研究生院課程VLSI測試與可測試性設(shè)計.ppt
