飲料自動(dòng)售賣機(jī)設(shè)計(jì)含開題及8張CAD圖

飲料自動(dòng)售賣機(jī)設(shè)計(jì)含開題及8張CAD圖,飲料,自動(dòng),售賣,設(shè)計(jì),開題,cad 本科生畢業(yè)論文（設(shè)計(jì)）英文原文原文出處：DOUGLASLP.VHDL：programming by exampleMNew York：McGrawHill Professional2002FOREWORDVHDL has been at the heart of electronic design productivity since initial ratification by the IEEE in 1987. For almost 15 years the electronic design automation industry has expanded the use of VHDL from initial concept of design documentation, to design implementation and func tional verification. It can be said that VHDL fueled modern synthesis technology and enabled the development of ASIC semiconductor compa nies. This book has served as the authoritative source of practical information on the use of VHDL for users of the language around the world.The use of VHDL has evolved and its importance increased as semi conductor devices dimensions have shrunk. Not more than 10 years ago it was common to mix designs described with schematics and VHDL. But as design complexity grew, the industry abandoned schematics in favor of the hardware description language only. The successive revisions of this book have always kept pace with the industrys evolving use of VHDL.The fact that VHDL is adaptable is a tribute to its architecture. The industry has seen the use of VHDLs package structure to allow design ers, electronic design automation companies and the semiconductor indus try to experiment with new language concepts to ensure good design tool and data interoperability. When the associated data types found in the IEEE 1164 standard were ratified, it meant that design data interoper ability was possible.All of this was facilitated by industry backing in a consortium of systems, electronic design automation and semiconductor companies now known as Accellera.And when the ASIC industry needed a standard way to convey gate-level design data and timing information in VHDL, one of Accelleras progenitors (VHDL International) sponsored the IEEE VHDL team to build a companion standard. The IEEE 1076.4 VITAL (VHDL Initiative Towards ASIC Libraries) was created and ratified as offers designers a single language flow from concept to gate-level signoff.In the late 90s, the Verilog HDL and VHDL industry standards teams collaborated on the use of a common timing data such as IEEE 1497 SDF, set register transfer level (RTL) standards and more to improve design methodologies and the external connections provided to the hardware description languages.But from the beginning, the leadership of the VHDL community has assured open and internationally accredited standards for the electronic design engineering community. The legacy of this teams work continues to benefit the design community today as the benchmark by which one measures openness.The design community continues to see benefits as the electronic design automation community continues to find new algorithms to work from VHDL design descriptions and related standards to again push designer productivity.And, as a new generation of designers of programmable logic devices move to the use of hardware description languages as the basis of their design methodology, there will be substantial growth in the number of VHDL users.This new generation of electronic designers, along with the current designers of complex systems and ASICs, will find this book invaluable . Updated with current ue of the standard, all will benefit from the years of use that have made the VHDL language the underpinning of successful electronic design.Introduction to VHDLThe VHSIC Hardware Description Language is an industry standard language used to describe hardware from the abstract to the concrete level. VHDL resulted from work done in the 70s and early 80s by the U.S. Department of Defense. Its roots are in the ADA language, as will be seen by the overall structure of VHDL as well as other VHDL statements.VHDL usage has risen rapidly since its inception and is used by literally tens of thousands of engineers around the globe to create sophisticated electronic products. This chapter will start the process of easing the reader into the complexities of VHDL. VHDL is a powerful language with numerous language constructs that are capable of describing very complex behavior. Learning all the features of VHDL is not a simple task. Complex features will be introduced in a simple form and then more complex usage will be described.In 1986, VHDL was proposed as an IEEE standard. It went through a number of revisions and changes until it was adopted as the IEEE 1076 standard in December 1987. The IEEE 1076-1987 standard VHDL is the VHDL used in this book.(Appendix D contains a brief description of VHDL 1076-1993.) All the examples have been described in IEEE 1076 VHDL, and compiled and simulated with the VHDL simulation environment from Model Technology Inc. VHDL TermsBefore we go any further, lets define some of the terms that we use throughout the book. These are the basic VHDL building blocks that are used in almost every description, along with some terms that are redefined in VHDL to mean something different to the average designer. Entity. All designs are expressed in terms of entities. An entity is the most basic building block in a design. The uppermost level of the design is the top-level entity. If the design is hierarchical, then the top-level description will have lowerlevel descriptions contained in it. These lower-level descriptions will be lowerlevel mentities contained in the top-level entity description.Architecture. All entities that can be simulated have an architecturedescription. The architecture describes the behavior of the entity. A single entity can have multiple architectures. One architecture might be behavioral while another might be a structural description of the design.Configuration. A configuration statement is used to bind a component instance to an entity-architecture pair. A configuration can be considered like a parts list for a design. It describes which behavior to use for each entity, much like a parts list describes which part to use for each part in the design.Package. A package is a collection of commonly used data types andsubprograms used in a design. Think of a package as a toolbox that containstools used to build designs.Driver. This is a source on a signal. If a signal is driven by two sources, then when both sources are active, the signal will have two drivers.Bus. The term “bus” usually brings to mind a group of signals or a particular method of communication used in the design of hardware. In VHDL, a bus is a special kind of signal that may have its drivers turned off.Attribute. An attribute is data that are attached to VHDL objects or predefined data about VHDL objects. Examples are the current drive capability of a buffer or the maximum operating temperature of the device.Generic. A generic is VHDLs term for a parameter that passes information to an entity. For instance, if an entity is a gate level model with a rise and a fall delay, values for the rise and fall delays could be passed into the entity with generics.Process. A process is the basic unit of execution in VHDL. All operations that are performed in a simulation of a VHDL description are broken into single or multiple processes.Describing Hardware in VHDLVHDL Descriptions consist of primary design units and secondary design units. The primary design units are the Entity and the Package. The secondary design units are the Architecture and the Package Body. Secondary design units are always related to a primary design unit. Libraries are collections of primary and secondary design units. A typical design usually contains one or more libraries of design units.EntityA VHDL entity specifies the name of the entity, the ports of the entity, and entityrelated information. All designs are created using one or more entities. Lets take a look at a simple entity example:ENTITY mux ISPORT ( a, b, c, d : IN BIT;s0, s1 : IN BIT; x, : OUT BIT);END mux;The keyword ENTITY signifies that this is the start of an entity statement. In the descriptions shown throughout the book, keywords of the language and types provided with the STANDARD package are shown in ALL CAPITAL letters. For instance, in the preceding example, the keywords are ENTITY, IS, PORT, IN, INOUT, and so on. The standard type provided is BIT. Names of user-created objects such as mux, in the example above, will be shown in lower case.The name of the entity is mux. The entity has seven ports in the PORT clause. Six ports are of mode INand one port is of mode OUT. The four data input ports (a, b, c, d) are of type BIT. The two multiplexer select inputs, s0 and s1, are also of type BIT. The output port is of type BIT. The entity describes the interface to the outside world. It specifies the number of ports, the direction of the ports, and the type of the ports. A lot more information can be put into the entity than is shown here, but this gives us a foundation upon which we can build more complex examples.ArchitecturesThe entity describes the interface to the VHDL model. The architecture describes the underlying functionality of the entity and contains the statements that model the behavior of the entity. An architecture is always related to an entity and describes the behavior of that entity. An architecture for the counter device described earlier would look like this:ARCHITECTURE dataflow OF mux ISSIGNAL select : INTEGER;BEGINselect = 0 WHEN s0 = 0 AND s1 = 0 ELSE1 WHEN s0 = 1 AND s1= 0 ELSE2 WHEN s0 = 0 AND s1 = 1 ELSE3;x = a AFTER 0.5 NS WHEN select = 0 ELSEb AFTER 0.5 NS WHENselect = 1 ELSEc AFTER 0.5 NS WHEN select = 2 ELSEd AFTER 0.5 NS;END dataflow;The keyword ARCHITECTURE signifies that this statement describes anarchitecture for an entity. The architecture name is dataflow. The entitythe architecture is describing is called mux.The reason for the connection between the architecture and the entity is that an entity can have multiple architectures describing the behavior of the entity. For instance, one architecture could be a behavioral description, and another could be a structural description.The textual area between the keyword ARCHITECTURE and the keyword BEGIN is where local signals and components are declared for later use.In this example signal select is declared to be a local signal.The statement area of the architecture starts with the keyword BEGIN.All statements between the BEGINand the ENDnetlist statement are calledconcurrent statements, because all the statements execute concurrently.Default ConfigurationsThe simplest form of explicit configuration is the default configuration. This configuration can be used for models that do not contain any blocks or components to configure. The default configuration specifies the configuration name, the entity being configured, and the architecture to be used for the entity. Following is an example of two default configurations shown by configurations big_count and small_count:LIBRARY IEEE;USE IEEE.std_logic_1164.ALL;ENTITY counter ISPORT(load, clear, clk : IN std_logic;PORT(data_in : IN INTEGER;PORT(data_out : OUT INTEGER);END counter;ARCHITECTURE count_255 OF counter ISBEGINPROCESS(clk)VARIABLE count : INTEGER := 0;BEGINIF clear = 1 THENcount := 0;ELSIF load = 1 THENcount := data_in;ELSEIF (clkEVENT) AND (clk = 1) AND(clkLAST_VALUE = 0) THENIF (count = 255) THENcount := 0;ELSEcount := count + 1;END IF;END IF;END IF;data_out = count;END PROCESS;END count_255;ARCHITECTURE count_64k OF counter ISBEGINPROCESS(clk)VARIABLE count : INTEGER := 0;BEGINIF clear = 1 THENcount := 0;ELSIF load = 1 THENcount := data_in;ELSEIF (clkEVENT) AND (clk = 1) AND(clkLAST_VALUE = 0) THENIF (count = 65535) THENcount := 0;ELSEcount := count + 1;END IF;END IF;END IF;data_out = count;END PROCESS;END count_64k;CONFIGURATION small_count OF counter ISFOR count_255END FOR;END small_count;CONFIGURATION big_count OF counter ISFOR count_64kEND FOR;END big_count;This example shows how two different architectures for a counter entity can be configured using two default configurations. The entity for the counter does not specify any bit width for the data to be loaded into the counter or data from the counter. The data type for the input and output data is INTEGER.With a data type of integer, multiple types of counters can be supported up to the integer representation limit of the host computer for the VHDL simulator. The two architectures of entity counter specify two different-sized counters that can be used for the entity. The first architecture, count_255, specifies an 8-bit counter. The second architecture, count_64k, specifies a 16-bit counter. The architectures specify a synchronous counter with a synchronous load and clear. All operations for the device occur with respect to the clock.Each of the two configurations for the entity specifies a different architecture for the counter entity. Lets examine the first configuration in more detail. The configuration design unit begins with the keyword CONFIGURATION and is followed by the name of the configuration. In this example, the name of the configuration is small_count. The keyword OF precedes the name of the entity BEGIN configured (counter). The next line of the configuration starts the block configuration section. The keyword FOR is followed by a name of the architecture to use for the entity being configured or the name of the block of the architecture that will be configured. Any component or block configuration information then existsbetween the FOR ARCHITECTURE clause and the matching END FOR.In this architecture, there are no blocks or components to configure; therefore, the block configuration area from the FOR clause to the END FOR clause is empty, and the default is used. The configuration is called the default configuration, because the default is used for all objects in the configuration.The first configuration is called small_count and binds architecture count_255 with entity counter to form a simulatable object. The second configuration binds architecture count_64k with entity counter and forms a simulatable object called big_count.第 9 頁(yè) 共 9 頁(yè)