基于單片機(jī)的水浴溫度檢測(cè)系統(tǒng)的軟件設(shè)計(jì)

基于單片機(jī)的水浴溫度檢測(cè)系統(tǒng)的軟件設(shè)計(jì),基于,單片機(jī),水浴,溫度,檢測(cè),系統(tǒng),軟件設(shè)計(jì) 畢業(yè)設(shè)計(jì)（論文）中英文文獻(xiàn) 題 目 S T C 8 9 C 5 2 芯 片 介 紹 專(zhuān) 業(yè) 名 稱(chēng) 電 子 信 息 工 程 班 級(jí) 學(xué) 號(hào) 0 7 8 2 0 5 3 3 3 學(xué) 生 姓 名 羅 東 祥 指 導(dǎo) 教 師 葉 愛(ài) 華 2011 年 3 月 9 日 STC89C52芯片介紹 （譯文）特點(diǎn)： *與MCS-51產(chǎn)品指令和引腳完全兼容 *8K字節(jié)可重擦寫(xiě)Flash閃速存儲(chǔ)器 *壽命：1000次擦寫(xiě)周期 *全靜態(tài)操作:0HZ-24MHZ *三級(jí)加密程序存儲(chǔ)器 *256*8字節(jié)內(nèi)部RAM *32個(gè)可編程I/O口線(xiàn) *3個(gè)16位定時(shí)/計(jì)數(shù)器 *8個(gè)中斷源 *可編程串行UART通道 *低功耗空閑和掉電模式 功能特性描述： STC89C52是一種低電壓，高性能CMOS8位單片機(jī)，片內(nèi)含8K BYTES的可反復(fù)擦寫(xiě)的只讀程序存儲(chǔ)器(EPROM),器件采用ATMEL公司的高密度、非易失性存儲(chǔ)技術(shù)生產(chǎn)，與標(biāo)準(zhǔn)的80C51和80C52產(chǎn)品的指令系統(tǒng)和引腳兼容，芯片擦寫(xiě)允許程序存儲(chǔ)器在系統(tǒng)內(nèi)部或一個(gè)普通的非易失存儲(chǔ)器的程序員所改寫(xiě)。片內(nèi)置通用8位中央處理器（CPU）和FLASH存儲(chǔ)單元，功能強(qiáng)大的STC89C52單片機(jī)適用于許多較為復(fù)雜控制應(yīng)用場(chǎng)合。 STC89C52提供以下標(biāo)準(zhǔn)功能：8K字節(jié)FLASH閃速存儲(chǔ)器，256字節(jié)內(nèi)部RAM，32個(gè)I/O口線(xiàn)，3個(gè)16位定時(shí)/計(jì)數(shù)器，一個(gè)6向兩級(jí)中斷結(jié)構(gòu)，一個(gè)全雙工串行通信口，片內(nèi)振蕩器及時(shí)時(shí)鐘電路：同時(shí)，STC89C52可降至0HZ的靜態(tài)邏輯操作，并支持兩種軟件可選的節(jié)電工作模式?？臻e方式停止CPU的工作，但允許RAM，定時(shí)/計(jì)數(shù)器，串行通信口及中斷系統(tǒng)繼續(xù)工作。掉電方式保存RAM中的內(nèi)容，但振蕩器停止工作并禁止其它所有部件工作直到下一個(gè)硬件復(fù)位。 引腳功能說(shuō)明 *VCC：電源電壓 *GND：地 *P0口：P0口是一組8位漏極開(kāi)路型雙向I/O口，也即地址/數(shù)據(jù)總線(xiàn)復(fù)用口。作為輸出口用時(shí)，每位能吸收電流的方式驅(qū)動(dòng)8個(gè)TTL邏輯門(mén)電路，對(duì)端口P0寫(xiě)“1”時(shí)，可作為高阻抗輸入端用。 在訪問(wèn)外部數(shù)據(jù)存儲(chǔ)器或程序存儲(chǔ)器時(shí)，這組口線(xiàn)分時(shí)轉(zhuǎn)換地址（低8位）和數(shù)據(jù)總線(xiàn)復(fù)用，在訪問(wèn)期間激活內(nèi)部上拉電阻。 在FLASH編程時(shí)，P0口接收指令字節(jié)，而在程序校檢時(shí)，輸出指令字節(jié)，校檢時(shí)，要求外接上拉電阻。 *P1口：P1是一個(gè)帶內(nèi)部上拉電阻的8位雙向I/O口，P1的輸出緩沖級(jí)可驅(qū)動(dòng)（吸收或輸出電流）4個(gè)TTL邏輯門(mén)電路。對(duì)端口寫(xiě)“1”，通過(guò)內(nèi)部的上拉電阻把端口拉倒高電平，此時(shí)可作輸入口。作輸入口使用，因?yàn)閮?nèi)部存在上拉電阻，某個(gè)引腳被外部信號(hào)拉低時(shí)會(huì)輸出一個(gè)電流（I）。 與STC89C51不同之處是，P1.0和P1.1還可分別作為定時(shí)/計(jì)數(shù)器2的外部計(jì)數(shù)輸入(P1.0/T2)和輸入(P1.1/T2EX),參見(jiàn)表1。 FLASH編程和程序校檢期間，P1接收8位地址. 表0 P1.0和P1.1的第二功能 *P2口：P2是一個(gè)帶有內(nèi)部上拉電阻的8位雙向I/O口，P2口，P2的輸出緩沖級(jí)可驅(qū)動(dòng)(吸收或輸出電流)4個(gè)TTL邏輯門(mén)電路.對(duì)端口P2寫(xiě)“1”，通過(guò)內(nèi)部的上拉電阻把端口拉到高電平,此時(shí)可作輸入口,作輸入口使用時(shí),因?yàn)閮?nèi)部存在上拉電阻。某個(gè)引腳被外部信號(hào)拉低時(shí)會(huì)輸出一個(gè)電流(I)。 在訪問(wèn)外部程序存儲(chǔ)器或16位地址的外部數(shù)據(jù)存儲(chǔ)器(例如執(zhí)行MOVX @DPTR指令)時(shí)，P2口輸出P2鎖存器的內(nèi)容。 FLASH編程或校檢時(shí)，P2亦接收高位地址和一些控制信號(hào)。 *P3口: P3口是一組帶有內(nèi)部上拉電阻的8位雙向I/O口，P3口輸出緩沖級(jí)可驅(qū)動(dòng)(吸收或輸出電流)4個(gè)TTL邏輯門(mén)電路。對(duì)P3口寫(xiě)入“1”時(shí)，它們被內(nèi)部上拉電阻拉高并可作為輸入端口。此時(shí)，被外部拉低的P3口將用上拉電阻輸出電流(I)。 P3口除了作為一般的I/O口線(xiàn)外,更重要的用途是它的第二功能，如下圖所示: P3口還接收一些用于FLASH閃速存儲(chǔ)器編程和程序校驗(yàn)的控制信號(hào)。 *RST: 復(fù)位輸入.當(dāng)振蕩器工作時(shí)，RST引腳出現(xiàn)兩個(gè)機(jī)器周期以上高電平將使單片機(jī)復(fù)位。 *ALE/[PSEN]: 注:[]表示反信號(hào) 當(dāng)外部程序存儲(chǔ)器或數(shù)據(jù)存儲(chǔ)器時(shí),ALE(地址鎖存允許)輸出脈沖用于鎖存。 地址的底8位字節(jié).一般情況下，ALE仍以時(shí)鐘振蕩頻率的1/6輸出固定的脈沖信號(hào),因此它可對(duì)外輸出時(shí)鐘或用于定時(shí)目的，要注意的是：每當(dāng)訪問(wèn)外部數(shù)據(jù)存儲(chǔ)器時(shí)將跳過(guò)一個(gè)ALE脈沖。 對(duì)FLASH存儲(chǔ)器編程期間,該引腳還用于輸入編程脈沖([PROG])。 如有必要，可通過(guò)對(duì)特殊功能寄存器(SFR)區(qū)中的8EH單元的D0位置位，可禁止ALE操作。該位置位后，只有一條MOVX和MOVC指令才能將ALE激活。此外，該引腳會(huì)被微弱抬高,單片機(jī)執(zhí)行外部程序時(shí)，應(yīng)設(shè)置ALE禁止位無(wú)效。 *[PSEN]：程序存儲(chǔ)允許[PSEN]輸出是外部程序存儲(chǔ)器(地址為0000H-FFFFH)，[EA]端必須保持低電平(接地)。須注意的是：如果加密位LBI被編程,復(fù)位時(shí)內(nèi)部會(huì)鎖存EA端狀態(tài)。 如EA端為高電平(接VCC端)，CPU則執(zhí)行內(nèi)部程序存儲(chǔ)器中的指令。 FLASH存儲(chǔ)器編程時(shí),該引腳加上+12V編程允許電源VPP，當(dāng)然這必須是該器件是使用12V的編程電壓VPP。 *XTAL1：振蕩器反相放大器的及內(nèi)部時(shí)鐘發(fā)生器的輸入端。 *XTAL2：振蕩器反相放大器的輸出端.。 特殊功能寄存器: 表1 STC89C52 SFR 映像及復(fù)位狀態(tài)。 在STC89C52片內(nèi)存儲(chǔ)器中，80H-FFH共128單元為特殊功能寄存器(SFE)，SFR的地址空間映像如表2所示： 并非所有的地址都被定義，從80H-FFH共128字節(jié)只有一部分被定義，還有一部分沒(méi)有定義。對(duì)沒(méi)有定義的單元讀寫(xiě)將是無(wú)效的，讀出的數(shù)據(jù)將部確定，而寫(xiě)入的數(shù)據(jù)也將丟失。 不應(yīng)將數(shù)據(jù)“1”寫(xiě)入未定義的單元,由于這些單元在將來(lái)的產(chǎn)品中可能賦予新的功能,在這種情況下，復(fù)位后這些單元數(shù)值總是“0”。 STC89C52除了與STC89C51所有的定時(shí)/計(jì)數(shù)器0和定時(shí)/計(jì)數(shù)器1外，還增加了一個(gè)定時(shí)/計(jì)數(shù)器2。定時(shí)/計(jì)數(shù)器2的控制和狀態(tài)位位于T2CON(參見(jiàn)表2)T2MOD(參見(jiàn)表3)，寄存器對(duì)(RCA02H，RCAP2L)是定時(shí)器2在16位捕獲方式或16位自動(dòng)重裝載方式下的捕獲/自動(dòng)重裝載寄存器。 表2 定時(shí)/計(jì)數(shù)器2控制寄存器T2CON 中斷寄存器 STC89C52有6個(gè)中斷源，2個(gè)中斷優(yōu)先級(jí),IE寄存器控制各中斷位，IP寄存器中6個(gè)中斷源的每一個(gè)可定為2個(gè)優(yōu)先級(jí)。 數(shù)據(jù)寄存器 STC89C52有256個(gè)字節(jié)的內(nèi)部RAM，80H-FFH高128個(gè)字節(jié)與特殊功能寄存器(SFR)地址是重疊的，也就是高128字節(jié)的RAM和特殊功能的地址是相同的，但物理上它們是分開(kāi)的。 當(dāng)一條指令訪問(wèn)7FH以上的內(nèi)部地址單元時(shí),指令中使用的尋址方式是不同的，也即尋址方式?jīng)Q定是訪問(wèn)高128字節(jié)RAM還是訪問(wèn)特殊功能寄存器。如果指令是直接尋址方式則為訪問(wèn)特殊功能寄存器。 例如，下面的直接尋址指令訪問(wèn)特殊功能寄存器0A0H(即P2口)地址單元。 MOV 0A0H,#DATA 間接尋址指令訪問(wèn)高128字節(jié)RAM，例如,下面的間接尋址指令中，R0的內(nèi)容為0A0H，則訪問(wèn)數(shù)據(jù)字節(jié)地址為0A0H,而不是P2口(0A0H)。 MOV @R0,#DATA 堆棧操作也是間接尋址方式，所以高128位數(shù)據(jù)亦可作為堆棧區(qū)使用。 定時(shí)器0和定時(shí)器1： STC89C52的定時(shí)器0和定時(shí)器1的工作方式與AT89C51相同。 定時(shí)器2: 定時(shí)器2是一個(gè)16位定時(shí)/計(jì)數(shù)器.它既可當(dāng)定時(shí)器使用,也可作為外部事件計(jì)數(shù)器使用,其工作方式由特殊功能寄存器T2CON(如表2)的C/T2位選擇。定時(shí)器2有三種工作方式： 捕獲方式：自動(dòng)重裝載(向上或向下計(jì)數(shù))方式和波特率發(fā)生器方式，工作方式由T2CON的控制位來(lái)選擇，參見(jiàn)表3。 表3 定時(shí)器2工作方式 定時(shí)器2由兩個(gè)8位寄存器TH2和TL2組成，在定時(shí)器工作方式中，每個(gè)機(jī)器周期TL2寄存器的值加1，由于一個(gè)機(jī)器周期由12個(gè)振蕩時(shí)鐘構(gòu)成，因此計(jì)數(shù)速率為振蕩頻率的1/12。 在計(jì)數(shù)工作方式時(shí),當(dāng)T2引腳上外部輸入信號(hào)產(chǎn)生由1至0的下降沿時(shí)，寄存器的值加1。在這種工作方式下,每個(gè)機(jī)器周期的5SP2期間,對(duì)外部輸入信號(hào)進(jìn)行采樣。若在第一個(gè)機(jī)器周期中采到的值為1，而在下一個(gè)機(jī)器周期中采道德值為0，則在緊跟著的下一個(gè)周期的S3P1期間寄存器加1。由于識(shí)別1至0的跳變需要2個(gè)機(jī)器周期(24個(gè)振蕩周期)，因此最高計(jì)數(shù)速率為振蕩頻率的1/24。為確保采樣的正確性，要求輸入的電平在變化前至少保持一個(gè)完整周期的時(shí)間，以保證輸入信號(hào)至少被采樣一次。 The introduction of STC89C52 Features ? Compatible with MCS-51? Products ? 8K Bytes of In-System Reprogrammable Flash Memory ? Endurance: 1,000 Write/Erase Cycles ? Fully Static Operation: 0 Hz to 24 MHz ? Three-level Program Memory Lock ? 256 x 8-bit Internal RAM ? 32 Programmable I/O Lines ? Three 16-bit Timer/Counters ? Eight Interrupt Sources ? Programmable Serial Channel ? Low-power Idle and Power-down Modes Description The STC89C52 is a low-power, high-performance CMOS 8-bit microcomputer with 8K bytes of Flash programmable and erasable read only memory (PEROM). The device is manufactured using Atmel’s high-density nonvolatile memory technology and is compatible with the industry-standard 80C51 and 80C52 instruction set and pin out. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel STC89C52 is a powerful microcomputer which provides a highly-flexible and cost-effective solution to many embedded control applications. The STC89C52 provides the following standard features: 8K bytes of Flash, 256 bytes of RAM, 32 I/O lines, three 16-bit timer/counters, a six-vector two-level interrupt architecture, a full-duplex serial port, on-chip oscillator, and clock circuitry. In addition, the STC89C52 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning. The Power-down mode saves the RAM contents but freezes the oscillator, disabling all other chip functions until the next hardware reset. Pin Description VCC Supply voltage. GND Ground. Port 0 Port 0 is an 8-bit open drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as highimpedance inputs. Port 0 can also be configured to be the multiplexed loworder address/data bus during accesses to external program and data memory. In this mode, P0 has internal pullups. Port 0 also receives the code bytes during Flash programming and outputs the code bytes during program verification. External pullups are required during program verification. Port 1 Port 1 is an 8-bit bi-directional I/O port with internal pullups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups. In addition, P1.0 and P1.1 can be configured to be the timer/counter 2 external count input (P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2EX), respectively, as shown in the following table. Port 1 also receives the low-order address bytes during Flash programming and verification. Port 2 Port 2 is an 8-bit bi-directional I/O port with internal pull ups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the internal pull ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pull ups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application, Port 2 uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash programming and verification. Port 3 Port 3 is an 8-bit bi-directional I/O port with internal pull ups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the internal pull ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pull ups. Port 3 also serves the functions of various special features of the STC89C52, as shown in the following table. Port 3 also receives some control signals for Flash programming and verification. RST Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device. ALE/PROG Address Latch Enable is an output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external data memory. If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode. PSEN Program Store Enable is the read strobe to external program memory. When the STC89C52 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. EA/VPP External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions. This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming when 12-volt programming is selected. XTAL1 Input to the inverting oscillator amplifier and input to the internal clock operating circuit. XTAL2 Output from the inverting oscillator amplifier. Table 1. STC89C52 SFR Map and Reset Values Special Function Registers A map of the on-chip memory area called the Special Function Register (SFR) space is shown in Table 1. Note that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect. User software should not write 1s to these unlisted locations, since they may be used in future products to invoke new features. In that case, the reset or inactive values of the new bits will always be 0. Timer 2 Registers Control and status bits are contained in registers T2CON (shown in Table 2) and T2MOD (shown in Table 4) for Timer 2. The register pair (RCAP2H, RCAP2L) are the Capture/Reload registers for Timer 2 in 16-bit capture mode or 16-bit auto-reload mode. Interrupt Registers The individual interrupt enable bits are in the IE register. Two priorities can be set for each of the six interrupt sources in the IP register. Data Memory The STC89C52 implements 256 bytes of on-chip RAM. The upper 128 bytes occupy a parallel address space to the Special Function Registers. That means the upper 128 bytes have the same addresses as the SFR space but are physically separate from SFR space. When an instruction accesses an internal location above address 7FH, the address mode used in the instruction specifies whether the CPU accesses the upper 128 bytes of RAM or the SFR space. Instructions that use direct addressing access SFR space. For example, the following direct addressing instruction accesses the SFR at location 0A0H (which is P2). MOV 0A0H, #data Instructions that use indirect addressing access the upper 128 bytes of RAM. For example, the following indirect addressing instruction, where R0 contains 0A0H, accessesthe data byte at address 0A0H, rather than P2 (whose address is 0A0H). MOV @R0, #data Note that stack operations are examples of indirect addressing, so the upper 128 bytes of data RAM are availableas stack space. Timer 0 and 1 Timer 0 and Timer 1 in the STC89C52 operate the same way as Timer 0 and Timer 1 in the STC89C52. Timer 2 Timer 2 is a 16-bit Timer/Counter that can operate as either a timer or an event counter. The type of operation is selected by bit C/T2 in the SFR T2CON (shown in Table 2). Timer 2 has three operating modes: capture, auto-reload (up or down counting), and baud rate generator. The modes are selected by bits in T2CON, as shown in Table 3. Timer 2 consists of two 8-bit registers, TH2 and TL2. In the Timer function, the TL2 register is incremented every machine cycle. Since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of the oscillator frequency. In the Counter function, the register is incremented in response to a 1-to-0 transition at its corresponding external input pin, T2. In this function, the external input is sampled during S5P2 of every machine cycle. When the samples show a high in one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected. Since two machine cycles (24 oscillator periods) are required to recognize a 1-to-0 transition, the maximum count rate is 1/24 of the oscillator frequency. To ensure that a given level is sampled at least once before it changes, the level should be held for at least one full machine cycle.