單片機(jī)溫度控制系統(tǒng)的研究

單片機(jī)溫度控制系統(tǒng)的研究,單片機(jī),溫度,控制系統(tǒng),研究 第一章 AT89C51應(yīng)用 單片機(jī)廣泛應(yīng)用于商業(yè)：諸如調(diào)制解調(diào)器，電動機(jī)控制系統(tǒng)，空調(diào)控制系統(tǒng)，汽車發(fā)動機(jī)和其他一些領(lǐng)域。這些單片機(jī)的高速處理速度和增強(qiáng)型外圍設(shè)備集合使得它們適合于這種高速事件應(yīng)用場合。然而，這些關(guān)鍵應(yīng)用領(lǐng)域也要求這些單片機(jī)高度可靠。健壯的測試環(huán)境和用于驗(yàn)證這些無論在元部件層次還是系統(tǒng)級別的單片機(jī)的合適的工具環(huán)境保證了高可靠性和低市場風(fēng)險(xiǎn)。Intel 平臺工程部門開發(fā)了一種面向?qū)ο蟮挠糜隍?yàn)證它的AT89C51 汽車單片機(jī)多線性測試環(huán)境。這種環(huán)境的目標(biāo)不僅是為AT89C51 汽車單片機(jī)提供一種健壯測試環(huán)境，而且開發(fā)一種能夠容易擴(kuò)展并重復(fù)用來驗(yàn)證其他幾種將來的單片機(jī)。開發(fā)的這種環(huán)境連接了AT89C51。本文討論了這種測試環(huán)境的設(shè)計(jì)和原理，它的和各種硬件、軟件環(huán)境部件的交互性，以及如何使用AT89C51。 1.1介紹 8 位AT89C51 CHMOS 工藝單片機(jī)被設(shè)計(jì)用于處理高速計(jì)算和快速輸入/輸出。MCS51 單片機(jī)典型的應(yīng)用是高速事件控制系統(tǒng)。商業(yè)應(yīng)用包括調(diào)制解調(diào)器，電動機(jī)控制系統(tǒng)，打印機(jī)，影印機(jī)，空調(diào)控制系統(tǒng)，磁盤驅(qū)動器和醫(yī)療設(shè)備。汽車工業(yè)把MCS51 單片機(jī)用于發(fā)動機(jī)控制系統(tǒng)，懸掛系統(tǒng)和反鎖制動系統(tǒng)。AT89C51 尤其很好適用于得益于它的處理速度和增強(qiáng)型片上外圍功能集，諸如：汽車動力控制，車輛動態(tài)懸掛，反鎖制動和穩(wěn)定性控制應(yīng)用。由于這些決定性應(yīng)用，市場需要一種可靠的具有低干擾潛伏響應(yīng)的費(fèi)用-效能控制器，服務(wù)大量時(shí)間和事件驅(qū)動的在實(shí)時(shí)應(yīng)用需要的集成外圍的能力，具有在單一程序包中高出平均處理功率的中央處理器。擁有操作不可預(yù)測的設(shè)備的經(jīng)濟(jì)和法律風(fēng)險(xiǎn)是很高的。一旦進(jìn)入市場，尤其任務(wù)決定性應(yīng)用諸如自動駕駛儀或反鎖制動系統(tǒng)，錯誤將是財(cái)力上所禁止的。重新設(shè)計(jì)的費(fèi)用可以高達(dá)500K 美元，如果產(chǎn)品族享有同樣內(nèi)核或外圍設(shè)計(jì)缺陷的話，費(fèi)用會更高。另外，部件的替代品領(lǐng)域是極其昂貴的，因?yàn)樵O(shè)備要用來把模塊典型地焊接成一個總體的價(jià)值比各個部件高幾倍。為了緩和這些問題，在最壞的環(huán)境和電壓條件下對這些單片機(jī)進(jìn)行無論在部件級別還是系統(tǒng)級別上的綜合測試是必需的。Intel Chandler 平臺工程組提供了各種單片機(jī)和處理器的系統(tǒng)驗(yàn)證。這種系統(tǒng)的驗(yàn)證處理可以被分解為三個主要部分。系統(tǒng)的類型和應(yīng)用需求決定了能夠在設(shè)備上執(zhí)行的測試類型。 1.2 AT89C51提供以下標(biāo)準(zhǔn)功能 4k 字節(jié)FLASH 閃速存儲器，128 字節(jié)內(nèi)部RAM，32 個I/O 口線，2 個16 位定時(shí)/計(jì)數(shù)器，一個5 向量兩級中斷結(jié)構(gòu)，一個全雙工串行通信口，片內(nèi)振蕩器及時(shí)鐘電路。同時(shí)，AT89C51 降至0Hz 的靜態(tài)邏輯操作，并支持兩種可選的節(jié)電工作模式。空閑方式體制CPU 的工作，但允許RAM，定時(shí)/計(jì)數(shù)器，串行通信口及中斷系統(tǒng)繼續(xù)工作。掉電方式保存RAM 中的內(nèi)容，但振蕩器體制工作并禁止其他所有不見工作直到下一個硬件復(fù)位。下1.1圖為AT89C51內(nèi)部結(jié)構(gòu)圖。 圖1.1 AT89C51內(nèi)部結(jié)構(gòu)圖 1.3引腳功能說明 ·Vcc：電源電壓 ·GND：地 ·P0 口：P0 口是一組8 位漏極開路型雙向I/O 口，也即地址/數(shù)據(jù)總線復(fù)用。作為輸出口用時(shí)，每位能吸收電流的方式驅(qū)動8 個TTL 邏輯門電路，對端口寫“1”可作為高阻抗輸入端用。在訪問外部數(shù)據(jù)存儲器或程序存儲器時(shí)，這組口線分時(shí)轉(zhuǎn)換地址（低8 位）和數(shù)據(jù)總線復(fù)用，在訪問期間激活內(nèi)部上拉電阻。在Flash 編程時(shí)，P0 口接受指令字節(jié)，而在程序校驗(yàn)時(shí)，輸出指令字節(jié)，校驗(yàn)時(shí)，要求外接上拉電阻。 ·P1 口：P1 是一個帶內(nèi)部上拉電阻的8 位雙向I/O 口，P1 的輸出緩沖級可驅(qū)動（吸收或輸出電流）4 個TTL 邏輯門電路。對端口寫“1”，通過內(nèi)部的上拉電阻把端口拉到高電平，此時(shí)可作輸入口。作為輸入口使用時(shí)，因?yàn)閮?nèi)部存在上拉電阻，某個引腳被外部信號拉低時(shí)會輸出一個電流（IIL）。Flash 編程和程序校驗(yàn)期間，P1 接受低8 位地址。 ·P2 口：P2 是一個帶有內(nèi)部上拉電阻的8 位雙向I/O 口，P2 的輸出緩沖級可驅(qū)動（吸收或輸出電流）4 個TTL 邏輯門電路。對端口寫“1”，通過內(nèi)部的上拉電阻把端口拉到高電平，此時(shí)可作輸入口。作為輸入口使用時(shí)，因?yàn)閮?nèi)部存在上拉電阻，某個引腳被外部信號拉低時(shí)會輸出一個電流（IIL）。在訪問外部程序存儲器或16 位四肢的外部數(shù)據(jù)存儲器（例如執(zhí)行MOVX @DPTR指令）時(shí)，P2 口送出高8 位地址數(shù)據(jù)，在訪問8 位地址的外部數(shù)據(jù)存儲器（例如執(zhí)行MOVX @ RI 指令）時(shí)，P2 口線上的內(nèi)容（也即特殊功能寄存器（SFR）區(qū)中R2 寄存器的內(nèi)容），在整個訪問期間不改變。Flash 編程和程序校驗(yàn)時(shí)，P2 也接收高位地址和其他控制信號。 ·P3 口：P3 是一個帶有內(nèi)部上拉電阻的8 位雙向I/O 口，P3 的輸出緩沖級可驅(qū)動（吸收或輸出電流）4 個TTL 邏輯門電路。對端口寫“1”，通過內(nèi)部的上拉電阻把端口拉到高電平，此時(shí)可作輸入口。作為輸入口使用時(shí)，因?yàn)閮?nèi)部存在上拉電阻，某個引腳被外部信號拉低時(shí)會輸出一個電流（IIL）。P3 口還接收一些用于Flash 閃速存儲器編程和程序校驗(yàn)的控制信號。 ·RST：復(fù)位輸入。當(dāng)振蕩器工作時(shí)，RST 引腳出現(xiàn)兩個機(jī)器周期以上高電平將使單片機(jī)復(fù)位。 ·ALE/PROG：當(dāng)訪問外部程序存儲器或數(shù)據(jù)存儲器時(shí)，ALE（地址鎖存允許）輸出脈沖用于鎖存地址的低8 位字節(jié)。即使不訪問外部存儲器，ALE 仍以時(shí)鐘振蕩頻率的1/6 輸出固定的正脈沖信號，因此它可對外輸出時(shí)鐘或用于定時(shí)目的。要注意的是，每當(dāng)訪問外部數(shù)據(jù)存儲器時(shí)將跳過一個ALE 脈沖。對Flash 存儲器編程期間，該引腳還用于輸入編程脈沖（PROG）。如有必要，可通過對特殊功能寄存器（SFR）區(qū)中的8EH 單元D0 位置位，可禁止ALE 操作。該位置位后，只有一條MOVX 和MOVC 指令A(yù)LE 才會被激活。此外，該引腳會被微弱拉高，單片機(jī)執(zhí)行外部程序時(shí)，應(yīng)設(shè)置ALE 無效。 ·PSEN：程序存儲允許輸出是外部程序存儲器的讀選通型號，當(dāng)89C51 由外部存儲器取指令（或數(shù)據(jù)）時(shí)，每個機(jī)器周期兩次PSEN 有效，即輸出兩個脈沖。在此期間，當(dāng)訪問外部數(shù)據(jù)存儲器，這兩次有效的PSEN 信號不出現(xiàn)。 ·EA/VPP：外部訪問允許。欲使CPU 僅訪問外部程序存儲器（地址為 0000H—FFFFH），EA 端必須保持低電平（接地）。需注意的是：如果加密位LB1 被編程，復(fù)位時(shí)內(nèi)部會鎖存EA 端狀態(tài)。如EA 端為高電平（接Vcc 端），CPU 則執(zhí)行內(nèi)部程序存儲器中的指令。Flash 存儲器編程時(shí)，該引腳加上+12v 的編程允許電源Vpp，當(dāng)然這必須是該器件使用12v 編程電壓Vpp。 ·XTAL1：振蕩器反相放大器及內(nèi)部時(shí)鐘發(fā)生器的輸入端。 ·XTAL2：振蕩器反相放大器的輸出端。89C51 中有一個用于構(gòu)成內(nèi)部振蕩器的高增益反相放大器，引腳XTAL1 和XTAL2分別是該放大器的輸入端和輸出端。這個放大器與作為反饋元件的片外石英晶體或陶瓷諧振器一起構(gòu)成自激振蕩器，振蕩電路參見圖5。外接石英晶體或陶瓷諧振器及電容C1、C2 接在放大器的反饋回路中構(gòu)成并聯(lián)振蕩電路。對電容C1、C2 雖沒有十分嚴(yán)格的要求，但電容容量的大小會輕微影響振蕩頻率的高低、振蕩器工作的穩(wěn)定性、起振的難易程度及溫度穩(wěn)定性，如果使用石英晶體，我們推薦電容使用30Pf±10 Pf，而如使用陶瓷諧振器建議選擇40Pf±10Pf。用戶也可以采用外部時(shí)鐘。這種情況下，外部時(shí)鐘脈沖接到XTAL1 端，即內(nèi)部時(shí)鐘發(fā)生器的輸入端XTAL2 則懸空。 ·掉電模式： 在掉電模式下，振蕩器停止工作，進(jìn)入掉電模式的指令是最后一條被執(zhí)行的指令，片內(nèi)RAM 和特殊功能寄存器的內(nèi)容在終止掉電模式前被凍結(jié)。推出掉電模式的唯一方法是硬件復(fù)位，復(fù)位后將重新定義全部特殊功能寄存器但不改變RAM 中的內(nèi)容，在Vcc 恢復(fù)到正常工作電平前，復(fù)位應(yīng)無效，且必須保持一定時(shí)間以使振蕩器重啟動并穩(wěn)定工作。89C51 的程序存儲器陣列是采用字節(jié)寫入方式編程的，每次寫入一個字符，要對整個芯片的EPROM 程序存儲器寫入一個非空字節(jié)，必須使用片擦除的方法將整個存儲器的內(nèi)容清楚。 第二章 編程方法 編程前，設(shè)置好地址、數(shù)據(jù)及控制信號，編程單元的地址加在P1 口和P2 口的P2.0—P2.3（11 位地址范圍為0000H——0FFFH），數(shù)據(jù)從P0口輸入，引腳P2.6、P2.7 和P3.6、P3.7 的電平設(shè)置見表6，PSEB 為低電平，RST保持高電平，EA/Vpp 引腳是編程電源的輸入端，按要求加上編程電壓，ALE/PROG引腳輸入編程脈沖（負(fù)脈沖）。編程時(shí)，可采用4—20MHz 的時(shí)鐘振蕩器，89C51 編程方法如下：在地址線上加上要編程單元的地址信號在數(shù)據(jù)線上加上要寫入的數(shù)據(jù)字節(jié)。激活相應(yīng)的控制信號。在高電壓編程方式時(shí)，將EA/Vpp 端加上+12v 編程電壓。每對Flash 存儲陣列寫入一個字節(jié)或每寫入一個程序加密位，加上一個ALE/PROG 編程脈沖。改變編程單元的地址和寫入的數(shù)據(jù)，重復(fù)1—5 步驟，知道全部文件編程結(jié)束。每個字節(jié)寫入周期是自身定時(shí)的，通常約為1.5ms?！?shù)據(jù)查詢89C51 單片機(jī)用數(shù)據(jù)查詢方式來檢測一個寫周期是否結(jié)束，在一個寫周期中，如需要讀取最后寫入的那個字節(jié)，則讀出的數(shù)據(jù)的最高位（P0.7）是原來寫入字節(jié)的最高位的反碼。寫周期開始后，可在任意時(shí)刻進(jìn)行數(shù)據(jù)查詢。 2.1Ready/Busy: 字節(jié)編程的進(jìn)度可通過Ready/Busy 輸出信號檢測，編程期間，ALE 變?yōu)楦唠娖健癏”后P3.4（Ready/Busy）端被拉低，表示正在編程狀態(tài)（忙狀態(tài)）。編程完成后，P3.4 變?yōu)楦唠娖奖硎緶?zhǔn)備就緒狀態(tài)。 ·程序校驗(yàn)：如果加密位LB、LB2 沒有進(jìn)行編程，則代碼數(shù)據(jù)可通過地址和數(shù)據(jù)線讀回原編寫的數(shù)據(jù)，采用下圖的電路，程序存儲器的地址由P1 口和P2 口的P2.0—P2.3 輸入，數(shù)據(jù)由P0 口讀出，P206、P2.7 和P3.6、P3.7 的控制信號見表6，PSEN 保持低電平，ALE、EA 和RST 保持高電平。校驗(yàn)時(shí)，P0 口必須接上10k 左右的上拉電阻。 圖2.1 編程電路 圖2.2校驗(yàn)電路 2.2芯片擦除 利用控制信號的正確組合(表6)并保持ALE/PROG 引腳10ms 的低電平脈沖寬度即可將EPROM 陣列(4k 字節(jié))和三個加密位整片擦除,代碼陣列在片擦除操作中將任何非空單元寫入”1”,這步驟需在編程之前進(jìn)行。 2.3讀片內(nèi)簽名字節(jié) 89C51 單片機(jī)內(nèi)有3 個簽名字節(jié),地址為030H、031H 和032H。于聲明該器件的廠商、號和編程電壓。讀簽名字節(jié)的過程和單元030H、031H 和032H的正常校驗(yàn)相仿，只需要將P3.6 和P3.7 保持低電平，返回值意義如下： (030H) = 1EH 聲明產(chǎn)品由ATMEL 公司制造。 (031H) = 51H 聲明為89C51 單片機(jī)。 (032H) = FFH 聲明為12V 編程電壓。 (032H) = 05H 聲明為5 編程電壓。 2.4 編程接口 采用控制信號的正確組合可對Flash 閃速存儲陣列中的每一代碼字節(jié)進(jìn)行寫入和存儲器的整片擦除，寫操作周期是自身定時(shí)的，初始化后它將自動定時(shí)到操作完成。微機(jī)接口實(shí)現(xiàn)兩種信息形式的交換。在計(jì)算機(jī)之外，由電子系統(tǒng)所處理的信息以一種物理信號形式存在，但在程序中，它是用數(shù)字表示的。任一接口的功能都可分為以某種形式進(jìn)行數(shù)據(jù)庫變換的一些操作，所以外部和內(nèi)部形式的轉(zhuǎn)換是由許多步驟完成的。模擬-數(shù)字轉(zhuǎn)換器（ADC）用來將連續(xù)變化信號變成相應(yīng)的數(shù)字量，這數(shù)字量可是可能性的二進(jìn)制數(shù)值中的一固定值。如果傳感器輸出不是連續(xù)變化的，就不需模擬-數(shù)字轉(zhuǎn)換。這種情況下，信號調(diào)理單元必須將輸入信號變換成為另一信號，也可直接與接口的下一部分，即微計(jì)算機(jī)本身的輸入輸出單元相連接。輸出接口采用相似的形式，明顯的差別在于信息流的方向相反；是從程序到外部世界。這種情況下，程序可稱為輸出程序，它監(jiān)督接口的操作并完成數(shù)字-模擬轉(zhuǎn)換器（DAC）所需數(shù)字的標(biāo)定。該子程序依次送出信息給輸出器件，產(chǎn)生相應(yīng)的電信號，由DAC 轉(zhuǎn)換成模擬形式。最后，信號經(jīng)調(diào)理（通常是放大）以形成適應(yīng)于執(zhí)行器操作的形式。在微機(jī)電路中使用的信號幾乎總是太小而不能被直接地連到“外部世界”，因而必須用某種形式將其轉(zhuǎn)換成更適宜的形式。接口電路部分的設(shè)計(jì)是使用微機(jī)的工程師所面臨最重要的任務(wù)之一。我們已經(jīng)了解到微機(jī)中，信號以離散的位形式表示。當(dāng)微機(jī)要與只有打開或關(guān)閉操作的設(shè)備相連時(shí)，這種數(shù)字形式是最有用的，這里每一位都可表示一開關(guān)或執(zhí)行器的狀態(tài)。為了解決實(shí)際問題，一個單片機(jī)不僅包括CPU，程序和數(shù)據(jù)存儲器，另外，它必須含有通過CPU 訪問外部信息的硬件。一旦CPU 收集到數(shù)據(jù)信息和流程，它必須能夠改變外部領(lǐng)域的一部分，這些硬件設(shè)備稱作外圍設(shè)備，它們是CPU 通往外部的窗口。 單片機(jī)可利用外圍設(shè)備中最基本的用于一般用途的I/O 接口，每個I/O 接口既可作為輸入端又可作為輸出端，每個I/O 接口的功能取決與程序初始化階段對數(shù)據(jù)方位寄存器相應(yīng)位進(jìn)行置一和清零操作，通過CPU 指令對數(shù)據(jù)寄存器相應(yīng)位進(jìn)行置一和清零來置一和清零輸出端口，同樣輸入端口邏輯位也可以通過CPU 指令訪問。一些類型的串行口單元允許CPU 與外部設(shè)備進(jìn)行串口通信，用串口位代替平行位進(jìn)行通信需要少許的I/O 口，這樣使通信費(fèi)用降低但速度也相對慢些。串口傳送可以同步也可以異步。 Chapter 1 The application of AT89C51 Microcontrollers are used in a multitude of commercial applications such as modems, motor-control systems, air conditioner control systems, automotive engine and among others. The high processing speed and enhanced peripheral set of these microcontrollers make them suitable for such high-speed event-based applications. However, these critical application domains also require that these microcontrollers are highly reliable. The high reliability and low market risks can be ensured by a robust testing process and a proper tools environment for the validation of these microcontrollers both at the component and at the system level. Intel Plaform Engineering department developed an object-oriented multi-threaded test environment for the validation of its AT89C51 automotive microcontrollers. The goals of thisenvironment was not only to provide a robust testing environment for the AT89C51 automotive microcontrollers, but to develop an environment which can be easily extended and reused for the validation of several other future microcontrollers. The environment was developed in conjunction with Microsoft Foundation Classes (AT89C51). The paper describes the design and mechanism of this test environment, its interactions with various hardware/software environmental components, and how to use AT89C51. 1.1 Introduction The 8-bit AT89C51 CHMOS microcontrollers are designed to handle high-speedcalculations and fast input/output operations. MCS 51 microcontrollers are typically used for high-speed event control systems. Commercial applications include modems,motor-control systems, printers, photocopiers, air conditioner control systems, disk drives,and medical instruments. The automotive industry use MCS 51 microcontrollers in engine-control systems, airbags, suspension systems, and antilock braking systems (ABS). The AT89C51 is especially well suited to applications that benefit from its processing speed and enhanced on-chip peripheral functions set, such as automotive power-train control, vehicle dynamic suspension, antilock braking, and stability control applications. Because of these critical applications, the market requires a reliable cost-effective controller with a low interrupt latency response, ability to service the high number of time and event driven integrated peripherals needed in real time applications, and a CPU with above average processing power in a single package. The financial and legal risk of having devices that operate unpredictably is very high. Once in the market, particularly in mission criticalapplications such as an autopilot or anti-lock braking system, mistakes are financiallyprohibitive. Redesign costs can run as high as a $500K, much more if the fix means 2 back annotating it across a product family that share the same core and/or peripheral design flaw. In addition, field replacements of components is extremely expensive, as the devices are typically sealed in modules with a total value several times that of the component. To mitigate these problems, it is essential that comprehensive testing of the controllers be carried out at both the component level and system level under worst case environmental and voltage conditions.This complete and thorough validation necessitates not only a well-defined process but also a proper environment and tools to facilitate and execute the mission successfully.Intel Chandler Platform Engineering group provides post silicon system validation (SV) of various micro-controllers and processors. The system validation process can be broken into three major parts.The type of the device and its application requirements determine which types of testing are performed on the device. 1.2 The AT89C51 provides the following standard features 4Kbytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bittimer/counters, a five vector two-level interrupt architecture,a full duple ser -ial port, on-chip oscillator and clock circuitry.In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters,serial port and interrupt sys -tem to continue functioning. The Power-down Mode saves the RAM contents but freezes the oscil –lator disabling all other chip functions until the next hardware reset. Figure 1.2 Block Diagram 1.3 Pin Description VCC Supply voltage. GND Ground. Port 0：Port 0 is an 8-bit open-drain bi-directional I/O port. As an output port, each pin cansink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as highimpedance inputs.Port 0 may also be configured to be the multiplexed loworder address/data busduring accesses to external program and data memory. In this mode P0 has internalpullups.Port 0 also receives the code bytes during Flash programming,and outputs the codebytes during program verification. External pullups are required during programverification. Port 1：Port 1 is an 8-bit bi-directional I/O port with internal pullups.The Port 1 output buffers can sink/so -urce four TTL inputs.When 1s are written to Port 1 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups.Port 1 also receives the low-order address bytes during Flash programming and verification. Port 2：Port 2 is an 8-bit bi-directional I/O port with internal pullups.The Port 2 outputbuffers can sink/source four TTL inputs.When 1s are written to Port 2 pins they arepulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pullups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pullups.Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX@DPTR). In this application, it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register.Port 2 also receives the high-order address bits and some control signals durin Flash programming and verification. Port 3：Port 3 is an 8-bit bi-directional I/O port with internal pullups.The Port 3 outputbuffers can sink/sou -rce four TTL inputs.When 1s are written to Port 3 pins they are pulled high by the internal pullups and can be used as inputs. As inputs,Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups. Port 3 also serves the functions of various special featuresof the AT89C51 as listed below: RST：Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device. ALE/PROG：Address Latch Enable output pulse for latching the low byte of the address duringaccesses to external memory.This pin is also the program pulse input (PROG) during Flash programming.In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency,and may be used for external timing or clocking purposes. Note, however, that one ALEpulse is skipped duri -ng each access to external DataMemory.If desired, ALE operationcan be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active onlyduring a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Settingthe ALE-disable bit has no effect if the microcontroller is in external execution mode. PSEN：Program Store Enable is the read strobe to external program memory. When theAT89C51 is executing code from external program memory, PSEN is activated twiceeach machine cycle, except that two PSEN activations are skipped during each access toexternal data memory. EA/VPP：External Access Enable. EA must be strapped to GND in order to enable the deviceto fetch code from external program memory locations starting at 0000H up to FFFFH.Note, however, that if lock bit 1 is programmed, EA will be internally latched onreset.EA should be strapped to VCC for internal program executions. This pin alsreceives the 12-volt programming enable voltage (VPP) during Flash programming, forparts that require 12-volt VPP. XTAL1：Input to the inverting oscillator amplifier and input to the internal clock operatingcircuit. XTAL2 ：Output from the inverting oscillator amplifier.Oscillator CharacteristicsXTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifierwhich can be configured for use as an on-chip oscillator, as shown in Figure 1. Either aquartz crystal or ceramic resonator may be used. To drive the device from an externalclock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2.There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed. Idle Mode In idle mode, the CPU puts itself to sleep while all the onchip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. It should be noted that when idle is terminated by a hard ware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory. Power-down Mode In the power-down mode, the oscillator is stopped, and the instruction that invokes power-down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power-down mode is terminated. The only exit from power-down is a hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize.The AT89C51 code memory array is programmed byte-bybyte in either programming mode. To program any nonblank byte in the on-chip Flash Memory, the entire memory must be erased using the Chip Erase Mode. Chapter2 Programming Algorithm Before programming the AT89C51, the address, data and control signals should be set up according to the Flash programming mode table and Figure 3 and Figure 4. To program the AT89C51, take the following steps.1. Input the desired memory location on the address lines.2. Input the appropriate data byte on the data lines. 3. Activate the correct combination of control signals. 4. Raise EA/VPP to 12V for the high-voltage programming mode. 5. Pulse ALE/PROG once to program a byte in the Flash array or the lock bits. The byte-write cycle is self-timed and typically takes no more than 1.5 ms. Repeat steps 1 through 5, changing the address and data for the entire array or until the end of the object file is reached. Data Polling: The AT89C51 features Data Polling to indicate the end of a write cycle. During a write cycle, an attempted read of the last byte written will result in the complement of the written datum on PO.7. Once the write cycle has been completed, true data are valid on all outputs, and the next cycle may begin. Data Polling may begin any time after a write cycle has been initiated. 2.1 Ready/Busy: The progress of byte programming can also be monitored by the RDY/BSY output signal. P3.4 is pulled low after ALE goes high during programming to indicate BUSY. P3.4 is pulled high again when programming is done to indicate READY. Program Verify: If lock bits LB1 and LB2 have not been programmed, the programmed code data can be read back via the address and data lines for verification. The lock bits cannot be verified directly. Verification of the lock bits is achieved by observing that their features are enabled. Figure 2.1 Programming the Flash Figure 2.2 Verifying the Flash 2.2 Chip Erase The entire Flash array is erased electrically by using the proper combination of control signals and by holding ALE/PROG low for 10 ms. The code array is written with all “1”s. The chip erase operation must be executed before the code memory can be re-programmed. 2.3 Reading the Signature Bytes The signature bytes are read by the same procedure as a normal verification of locations 030H, 031H, and 032H, except that P3.6 and P3.7 must be pulled to a logic low. The values returned areas follows. (030H) = 1EH indicates manufactured by Atmel (031H) = 51H indicates 89C51 (032H) = FFH indicates 12V programming (032H) = 05H indicates 5V programming 2.4 Programming Interface Every code byte in the Flash array can be written and the entire array can be erased by using the appropriate combination of control signals. The write operation cycle is selftimed and once initiated, will automatically time itself to completion. A microcomputer interface converts information between two forms. Outside the microcomputer the information handled by an electronic system exists as a physical signal, but within the program, it is represented numerically. The function of any interface can be broken down into a number of operations which modify the data in some way, so that the process of conversion between the external and internal forms is carried out in a number of steps. An analog-to-digital converter(ADC) is used to convert a continuously variable sig